1) Field of the Invention
This invention relates generally to floating gate memory devices such as an array of flash electrically erasable and programmable read-only memory devices (EEPROMS) and more particularly, the present invention is directed to a method for manufacturing a Snap-Back Flash memory cell that uses a snap-back erase operation that prevents cycling-induced electron and hole trapping in the tunneling oxide of flash EEPROMS.
2) Background of the Invention
Flash EEPROMS have recently emerged as an important memory device by combining the advantages of EPROM density with EEPROM electrical erasability. Such flash EEPROM's provide electrical erasing and a small cell size. FIG. 1A illustrates a prior art cross-sectional view of a flash EEPROM cell 12. The EEPROM cell is formed of a substrate 10, typically of a p-type conductivity, having embedded therein an n+ drain region 14 and a n-type double-diffused source region 16. See E.g., U.S. Pat. No. 5,485,423(Tang et al.).
A relatively thin gate dielectric layer 22 (i.e., tunnel oxide or an oxide having a uniform thickness of about 100 .ANG.) is interposed between the top surface of the substrate 10 and a conductive polysilicon floating gate 24. A polysilicon control gate 26 is insulated above the floating gate 24 by an inter-poly dielectric 28. A channel region 30 in the substrate 10 separates the drain region 14 and the source region 16 Further, there are provided terminal pins 15, 25, and 13 for applying a source voltage Vs to the source region 16, a gate voltage Vg to the control gate 26, and a drain voltage Vd to the drain region 14, respectively.
In conventional operation, the flash EEPROM cell (i.e., NON-snap-back flash cell) of FIG. 1A is "programmed" by applying a relatively high voltage V, (approximately +9 volts) to the control gate via the terminal pin 25 and a moderately high voltage Vd (approximately +5 volts) to the drain region 14 via the terminal pin 13 in order to produce "hot" (high energy) electrons in the channel 30 near the drain region 14. The source region 16 is connected to a ground potential (Vs=0) via the terminal pin 15. The hot electrons are generated and accelerated across the gate dielectric 22 and onto the floating gate 24 and become trapped in the floating gate since the floating gate is surrounded by insulators. As a result, the floating gate threshold may be increased by three to five volts. This change in the threshold voltage, or channel conductance, of the cell created by the trapped hot electrons is what causes the cell to be programmed.
In order to erase the flash EEPROM cell of FIG. 1A, a positive voltage Vs is applied to the source region 16 via the terminal pin 15 while the control gate 26 via the terminal pin 25 is either grounded (Vg=0) or biased to a negative voltage dependent upon whether the positive voltage Vs applied to the source region 16 has a value of +12 V or +5 V In a "12 Volt flash EEPROM" device, the bias condition of Vs=+12V and Vg=0is used. In a "5 Volt Only flash EEPROM" device, the bias condition of Vs=+5 V and Vg=-8.5 V is used. The drain region 14 is usually allowed to float. Under either of these conditions, a strong electric field is developed across the tunnel oxide between the floating gate and the source region. The electrons trapped in the floating gate flow toward a cluster at the portion of the floating gate overlying the n+-type source region 16 and are extracted from the floating gate 24 to the source region 16 by way of Fowler-Nordheim (F-N) tunneling.
However, some of the electrons 21 will remain trapped in the tunnel oxide 22 adjacent the top surface of the substrate 10 as depicted in FIG. 1A. This electron and hole trapping will occur in the whole memory array and will tend to increase the erase time as a function of the number of program/erase cycles. As the number of program/erase cycles goes beyond the 100,000 number, the erase time required to erase every cell in the entire memory array to a certain threshold V.sub.T in order to pass the erase verify mode of operation will exceed the time limit of 10 seconds. It is generally assumed that if the entire memory array cannot be erased within the time limit of 10 seconds (i.e., 1 pulse/10 ms or 1,000 pulses), a cycling failure is considered to have occurred.
Therefore, the problem of electron and hole trapping in the tunneling oxide to reduce the tunneling electric field for such conventional EEPROM devices is of a major concern since it causes the erase time to be prolonged beyond the limit of 10 seconds (i.e., 1 pulse/10 ms), thereby significantly limiting the endurance of the cells. As used herein, the term "endurance" refers to the number of times the memory cells in the array may be re-programmed and erased. Consequently, the electron and hole trapping problem greatly reduces the endurance of the cells to be less than 100,000. In addition, the hole trapping caused by F-N tunneling current is also a serious issue. The hole trapping in the tunnel oxide will cause the Vt window opening and erratic bit.
In addition, some EEPROMS devices use Fowler-Nordheim (FN) tunneling in both the erase and program cycles. The above electron and hole trapping problem slows the program cycle also. FIGS. 2A-2C, show the conventional square pulse waveforms used in conventional EEPROM erase cycles. The inventor realized that the electron and hole trapping problem could be reduced by modifying the conventional waveforms for erase cycle. Furthermore, the inventor realized that better methods must be developed to fabricate a Snap-back EEPROM cell that are specially designed for snap-back operation.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature U.S. Pat. No. 5,607,869(Yamazaki) and U.S. Pat. No. 5,427,963(Richart et al.) that show methods of making asymmetric Lightly doped source transistors used in conventional non-snap-back cells. U.S. Pat. No. 5,485,423 (Tang) shows a method for applying a relative low positive voltage to a source region of an EEPROM during the erase cycle. "Different Dependence of Band to Band and Fowler-Nordheim Tunneling on Source Doping concentration of an N-MOSFET", by Yuan Tang et al., IEEE Electron Device Letters, vol. 17, No. 11, November 1996, pp. 525-526, discuss the FN tunneling as a function of source doping.
However, there exists a need for a new method to fabricate a Flash EEPROM cell this is specially designed for a SNAP-Back erase operation.